Merge stable-1.8 into master

test: disable pmem2_map_prot devdax exec test

Conflicts:
	src/libpmem/ppc64/platform_generic.c
	src/libpmemobj/heap.c
	src/test/obj_ctl_stats/obj_ctl_stats.c

test: fix pmem_deep_persist match

examples: fix pmem2 redo example fd leak

pmem: (PPC) call msync instead flush on valgrind

Ref: #4852

current version of Valgrind doesn't recognize ppc fence instruction

clean away __pycache__ dirs

pmem2: ndctl get size

common: improve performance of os_posix_fallocate on windows

obj: fix run allocated recalculation

pmem2: separate ravl map module and map.c

Fix data cache flush on ppc64

examples: add gitignore to multiple map example

pmem2: fix get alignment funcs

Move ravl map module implementation from map.c into separate files
ravl_interval.c and ravl_interval.h.
Effectively map.c passes an address of pmem2_map structure and two
points on a number line as ravl_interval structure.
Those points are abstraction for interval with following boundaries
(address, address + size).
The reason for the separation is that the pmem2_vm_reservation feature
will be using ravl tree in the future.

common: fix freebsd CI

pmem2: ndctl get alignment

common: fix freebsd CI

check that errno is set for PMEM2_E_ERRNO

The dcbst instruction doesn't flush a cache block correctly because it
doesn't mark that block as clean on Power 9, see Manual "POWER9
Processor User’s Manual" page 66.
Replace dcbst with dcbf in order to fix this issue. This change requires
to replace lwsync with a hwsync too in order to cover for the usage of
dcbf.

Adopt the best practices according to the POWER ISA 3.1.

Fix bug #4843.

Signed-off-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>

pmem2: fix deep flush ret value

Ref: issues#4825

pmem2: ddax deep flush behavior changes

pmem2: read usc from region instead of interleave set